Fuse, memory incorporating same and method

ABSTRACT

A method of making a fuse and a fuse, together with systems and integrated circuits where the fuse provides benefits, are described. A fuse comprising a conductive material is formed on a substrate. A series of dielectric layers having a composite thickness is formed on the substrate and the fuse. The series of dielectric layers serves to insulate a series of conductive layers from each other. The conductive layers are disposed above portions of the substrate. An opening is formed extending through a passivation layer and the series of dielectric layers. The opening exposes a portion of the fuse. Another dielectric layer is formed on the fuse and the fuse may thereafter be programmed by directing a laser beam onto the fuse through the opening.

TECHNICAL FIELD

[0001] This invention relates in general to fuses having application toprogramming of integrated circuitry, and more particularly to fusesuseful for replacement of defective memory cells.

BACKGROUND OF THE INVENTION

[0002]FIG. 1 is a simplified cross-sectional view of a portion of anintegrated circuit 10. The integrated circuit 10 includes asemiconductor substrate 18 in which active circuitry, designatedgenerally by reference numeral 20, is fabricated. The active circuitry20 may implement a variety of devices, including a conventional memorydevice, such as a dynamic random access memory (“DRAM”) or a staticrandom access memory (“SRAM”).

[0003] Integrated circuits 10 incorporating active circuitry 20 thatform a memory device include large numbers of memory cells. In fact,because of the large number of memory cells, there is a significantprobability that at least some of the memory cells will be defective.Defective memory cells are typically discovered during testing andbefore packaging the integrated circuit 10. To avoid the need to discardmemory devices having a relatively small number of defective memorycells, techniques have been developed for the post-manufacturereplacement of defective memory cells with redundant memory cellsspecifically provided for that purpose. Typically, memory cells arereplaced in one or more groups of memory cells (i.e., rows or columns).

[0004] With further reference to FIG. 1, one technique for selectingdefective rows or columns of memory cells for replacement is to blow apattern of fuses to correspond to a defective row or column of memorycells. A typical fuse 25 is shown in FIG. 1. Blowing a combination ofthe fuses 25 causes data to be written to or read from redundant memorycells rather than the defective memory cells corresponding to thepattern of blown fuses.

[0005] The fuses 25 are typically formed as a layer of polysilicon 24 ona dielectric layer 21, which insulates the polysilicon layer 24 from thesubstrate 28 comprising the integrated circuit 10. One or more layers ofconductive material 22, such as a layer of tungsten silicide, is thenformed on the polysilicon layer 24. For example, the conductive layer 22may have a thickness of 1,200+/−200 angstroms and the polysilicon layer24 may have a thickness of 1,000+/−200 angstroms. Other types ofconductive material, such as metals, may be used for the conductivelayer 22 or the polysilicon layer 24. The conductive layer 22 is coveredby a thin layer of dielectric material 27 that is integrally formed witha relatively thick layer dielectric layer 30 having a thickness T₁. Afirst conductive layer 32 may then be fabricated on the surface of thedielectric layer 30. The conductive layer 32 and the dielectric layer 30may then be coated with another dielectric layer 34 having a thicknessof T₂ on which a second conductive layer 36 may be fabricated. If so,the conductive layer 36 and the dielectric layer 34 may then be coatedwith another dielectric layer 38 having a thickness T₃. The conductivelayers 32 and 36 typically comprise polysilicon, but may be realized asmetal layers.

[0006] In some applications, the fuses 25 are blown by focusing a laserbeam to vaporize the layer of conductive material 22. In these cases,the dielectric layer 27 is chosen to be transparent to the laser light,and the conductive material 22 is chosen to strongly absorb the laserlight. When the laser light is incident on the conductive material 22,the fuse 25 is blown by vaporizing the conductive material 22.Additionally, a series of other fuses 25 may be optionally blown at thistime to encode various data regarding the part being manufactured.

[0007] In other applications, the fuses 25 are blown by directing acurrent through selected fuses 25 that is sufficient to vaporize thelayer of conductive material 22. In either case, precise control of thethickness of the dielectric layer 27 overlying the fuse 25 is criticalto successfully blowing the fuse 25. When the dielectric layer 27 is toothick, the fuse 25 may not blow or may blow but also create a craterbeneath the fuse 25 because the vaporized fusible material is confined.When the dielectric layer 27 is too thin, the fuse 25 may merely meltand then re-solidify to form a conductive stringer. Alternatively, thefuse 25 may be partially melted and partially vaporized, causingconductive, molten material to be deposited in undesirable locations.This can result in circuit malfunction.

[0008] The fuse 25 is typically exposed so that it can be blown with alaser by etching the dielectric layers 30, 34, 38 as shown in FIG. 1.The etching of the dielectric layer 30 is stopped just above the fuse25, thereby forming the dielectric layer 27. The etching processtypically is stopped when the layer of dielectric material 27 on thefuse 25 is about 2,000 to 3,000 angstroms. When the composite thicknessof the dielectric layers 30, 34, 38 is, for example, four microns, a2,500 angstrom thick dielectric layer 27 is about 6.25% of the compositethickness. Thus, etching the dielectric layers 30, 34, 38 so that thedielectric layer 27 has a thickness in the acceptable range of2,000-3,000 angstroms requires control of the etching process within1.25%, ie., 6.25%+/−1.25%. Currently used etching processes are capableof etching to 2,500+/−500 angstroms as long as the composite thicknessof the dielectric layers 30, 34, 38 is not significantly greater thanfour microns. However, increasing circuit complexity requires additionalconductive layers for forming interconnections and therefore additionaldielectric layers formed between the conductive layers. As the compositethickness increases, it is increasingly difficult to stop the etching ofthe dielectric layers when the dielectric layer 27 remaining on the fuse25 has the correct thickness. Variations in the composite thicknessacross the substrate 28 also increase with increases in the compositethickness of the dielectric layers, as do wafer-to-wafer variations andvariations in etch rates, both across a wafer and from wafer to wafer.

[0009] There is therefore a need for a technique to provide fuses oncomplex integrated circuits having the correct thickness of dielectricmaterial on the fusible material.

SUMMARY OF THE INVENTION

[0010] Briefly stated, embodiments of the present invention encompassfuses and methods of making fuses, together with systems and integratedcircuits where the fuses provide benefits. The fuses are made by amethod that provides control over the thickness of a dielectric layerformed on the fuse material, irrespective of the thickness of dielectriclayers previously formed on the fuse. The resulting fuses maintain theelectrical and mechanical characteristics needed in order to be able toblow the fuses reliably and with good fuse-to-fuse repeatability.

[0011] A fuse comprising a conductive material is formed on a substrateand a series of dielectric layers having a composite thickness areformed on the substrate and the fuse. The series of dielectric layersserves to insulate a series of conductive layers from each other. Theconductive layers are formed above portions of the substrate. An openingis formed that extends through the series of dielectric layers. Theopening exposes a portion of the fuse. A dielectric layer having acontrolled thickness is formed on the series of dielectric layers andthe fuse.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a simplified side cross-sectional view of a portion ofan integrated circuit according to the prior art.

[0013]FIG. 2 is a simplified side cross-sectional view of a portion ofan integrated circuit at one stage in processing according to anembodiment of the present invention.

[0014]FIG. 3 is a flow chart of a process for manufacturing anintegrated circuit according to an embodiment of the present invention.

[0015]FIG. 4 is a simplified side cross-sectional view of a portion ofan integrated circuit at a later stage in processing according to anembodiment of the present invention.

[0016]FIG. 5 is a simplified side cross-sectional view of a portion ofan integrated circuit at a still later stage in processing according toan embodiment of the present invention.

[0017]FIG. 6 is a simplified block diagram of a memory employing fusesin accordance with an embodiment of the invention.

[0018]FIG. 7 is a simplified block diagram of a computer using anintegrated circuit manufactured according to an embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

[0019] As the complexity of integrated circuits increase, for example,for memory arrays having 16 megabytes or more of storage capacity, theneed also increases for progressively more complex interconnections. Tomeet these needs, a series of interconnections comprising conductivelayers separated by dielectric layers is required.

[0020]FIG. 2 illustrates an example of an integrated circuit 40 that isidentical to the integrated circuit 10 of FIG. 1 except that it includesadditional conductive and dielectric layers. More specifically, theintegrated circuit 40 includes additional conductive layers 40, 44 and48 separated from each other and insulated by a series of additionaldielectric layers 42, 46, 50 and 52, however, more or fewer conductiveand intervening dielectric layers may be used. The conductive layers 32,36, 40, 44 and 48 typically are displaced laterally from the fuses 25 bytwenty five microns or more.

[0021] The conductive layers 32, 36, 40, 44 and 48 are conventional thinfilm, patterned conductive layers and may be formed by conventionalevaporation, sputtering or other deposition techniques. The dielectriclayers 34, 38, 42, 46 and 50 may be silicon dioxide deposited byconventional TEOS processes and may be conventionally densified, or mayhave other compositions or be formed by other processes includingatmospheric pressure chemical vapor deposition, low pressure chemicalvapor deposition, plasma-enhanced chemical vapor deposition and thelike. The dielectric layer 52 may be silicon nitride deposited byplasma-enhanced chemical vapor deposition. A composite thicknessT_(C)=T₁+T₂+T₃+T₄+T₅+T₆+T₇ of the dielectric layers 26, 30, 34, 38, 42,46, 50 and 52, in this example, could well be seven microns or as muchas eight microns, or a subset of these dielectric layers may providefour microns or more or less of composite thickness T_(C). A compositedielectric thickness T_(C) this large is too thick to form a thindielectric layer over the fuse 25 using the technique shown in FIG. 1.For a composite thickness of eight microns, for example, it would bepossible to control the thickness of the dielectric layer only to withinabout ±1,000 angstroms using current techniques. As a result, it wouldnot be possible to ensure that the dielectric layer had a thickness inthe range of 2,000-3,000 angstroms.

[0022]FIG. 3 is a flow chart of a process for manufacturing anintegrated circuit according to an embodiment of the present invention.FIG. 4 shows the structure being formed by steps 74 through 80 of theprocess. With reference to FIGS. 3 and 4, the process begins in step 74by applying and patterning a layer of photoresist 54 via conventionalprocesses. The patterned photoresist layer 54 covers the entire uppersurface of the top dielectric layer 52 except for an area overlying thefuse 25. In step 76, an anisotropic plasma etch is performed through theexposed area of the photoresist to form openings 56 extending throughthe dielectric layers 26, 30, 34, 38, 42, 46, 50 and 52. In other words,the plasma etching process etches much more rapidly through thethickness of the dielectric layers 26, 30, 34, 38, 42, 46, 50 and 52than it does laterally. The highly directional nature of the anisotropicetch allows the opening 56 to be formed with vertical sidewalls 58 asshown in FIG. 3. This results in a compact structure because the size ofthe opening 56 is maintained constant through the depth of thedielectric layers 26, 30, 34, 38, 42, 46, 50 and 52, rather than beingmuch broader in the layer 52 than in the dielectric layers 26 and 30that are closer to the substrate 28.

[0023] In one embodiment, the width (i.e., the distance into and out ofthe plane of FIG. 4) of the opening 56 is about ten microns. The length(ie., the lateral extent left and right in the plane of FIG. 4) of theopening 56 depends on the number of fuses that are being containedwithin the opening 56.

[0024] It has been discovered that the need to precisely control thedepth of etching through the series of dielectric layers 26, 30, 34, 38,42, 46, 50 and 52 is relaxed when the materials chosen for the fuse 25and the substrate 28 are not readily etched by the plasma etchingprocess used to etch the opening 56. The need to precisely control theetching process is further reduced when an anisotropic etch process isused to completely remove the dielectric layers including the dielectriclayer 26 on the fuse 25. While FIG. 1 shows the opening 56 as havingedges that coincide with the edges of the fuse 25, several fuses 25 maybe formed in one opening 56, and the edges of the fuses 25 or portionsof the substrate 28 between fuses 25 in a common opening 56 may beexposed to the etching process. Use of an anisotropic etch that alsodoes not etch the substrate 28 or the conductive layer 22 allowsdeliberate overetching of the opening 56 without undercutting the fusestructure 25, even when the edges of the fuse 25 and portions of thedielectric layer 21 are exposed to the etch. The fuse 25 and thesubstrate 28 can then act as etch stops.

[0025] Referring now to FIG. 3, when a query task 78 determines that theetching process of step 76 is complete, the anisotropic plasma etchprocess is stopped in step 80. Otherwise, the etching process iscontinued as in step 76. In one embodiment, the query task 78 may bebased on an endpoint detection that determines that the etching processhas reached the conductive layer 22, or, alternatively, the substrate28. In another embodiment, the query task 78 may allow passage of enoughtime to ensure that the anisotropic etching process of step 76 hasextended all of the openings 56 to all of the fuses 25.

[0026]FIG. 5 is a simplified side cross-sectional view of a portion ofan integrated circuit at a still later stage in processing according toan embodiment of the present invention. With reference now to FIGS. 3and 5, the opening 56 has been etched to completely remove thedielectric layer 26 from the fuse 25. In step 82, the photoresist layer54 of FIG. 4 is stripped. In step 84, a dielectric layer 60 is formed onall exposed surfaces, including the fuses 25. In one embodiment of thepresent invention, the dielectric layer 60 is a layer of silicon dioxideformed via a conventional TEOS process and having a thickness of 2,000to 3,000+/−300 angstroms, however, other dielectric materials and/orthicknesses may be employed. The process then ends and other processing,testing and packaging steps may be carried out.

[0027] By etching all of the openings 56 to expose all of the fuses 25and then depositing the dielectric layer 60, a uniformly thickdielectric layer 60 is provided on all of the fuses 25. This is trueregardless of variations in the composite dielectric layer thicknessT_(C) or etch rates across the wafer. This also does not result insignificant etching of the materials comprising the fuse 25 or thesubstrate 28. The characteristics of the fuses 25 and the parameters forblowing the fuses 25 are then uniform across the die or wafer. Thethickness of the dielectric layer 60 on the fuse 25 is independent ofvariations in the composite thickness T_(C) of the series of dielectriclayers 26, 30, 34, 38, 42, 46, 50 and 52 and is also independent ofvariations in etch rate in etching of the openings 56, either across anindividual device or wafer or from one wafer to another wafer.

[0028] Although the dielectric layer 60 is shown in FIG. 5 as lining thesides of the opening 56 and covering the exposed surface of thedielectric layer 52, it will be understood that it s only necessary forthe dielectric layer 60 to overlie the fuse 25.

[0029] Following completion of the structure shown in FIG. 5 accordingto the process of FIG. 2, wafer-level testing is carried out. In oneembodiment, defective rows and columns of memory cells are detected andthen fuses 25 are blown in a pattern corresponding to the defective rowsor columns by focusing 1047 nanometer laser light of appropriateintensity and duration to a spot size of about five microns on the fuse25 to vaporize the conductive materials 22 and 24. This allows devicesthat were manufactured with some defective memory cells to be useful asmemory devices.

[0030]FIG. 6 is a simplified block diagram of a memory device 90employing fuses 96, such as fuse the 25 of FIG. 5, in accordance with anembodiment of the invention. As shown in FIG. 6, the memory device 90includes a primary circuit 92 and an auxiliary circuit 94. The primarycircuit 92 includes a conventional memory array 93 having memory cellsarranged in rows and columns where individual cells in the memory array93 are accessed by addresses provided at address terminals 95. Data aretransferred to and from the memory array 93 via data terminals 97.

[0031] The auxiliary circuit 94 includes several fuse circuits 96 thatperform auxiliary functions, such as substituting redundant rows orcolumns 91 for defective rows or columns. While the primary circuit 92and the auxiliary circuit 94 are shown separately for clarity ofpresentation, one skilled in the art will recognize that the primarycircuit 92 and the auxiliary circuit 94 are typically integrated into acommon substrate.

[0032] In many such memory arrays 93, several redundant rows and columnsof memory cells 91 are provided to be used as substitutes for defectiverows and columns of memory cells in the memory array 93. When adefective bit location is identified, rather than treating the entirememory device 90 as defective, a redundant row or column 91 issubstituted for the row or column containing the defective memory cellor cells. This substitution is performed by assigning the address of thedefective row or column to the redundant row or column 91 such that,when an address corresponding to the defective row or column isreceived, the redundant row or column 91 is addressed instead.

[0033] To make substitution of the redundant row or column 91substantially transparent to a system employing the memory device 90,the memory device 90 includes an address detection circuit (notillustrated). The address detection circuit monitors the row and columnaddresses and, when the address of a defective row or column isreceived, enables the redundant row or column 91 instead.

[0034] One type of address detection circuit is a fuse-bank addressdetection circuit. An example of such a circuit and the application ofthis type of circuit to a memory integrated circuit is given in U.S.Pat. No. 5,583,463, issued on Dec. 10, 1996 to T. Merritt, which isincorporated herein by reference. Fuse-bank address detection circuitsemploy a bank of sense lines where each sense line corresponds to a bitof an address.

[0035] The sense lines are programmed by blowing fuses such as fuse 96of FIG. 6 in the sense lines in a pattern corresponding to the addressof the defective row or column. Addresses are then detected by firstapplying a test voltage across the bank of sense lines. Then, bits ofthe address are applied to the sense lines. When the pattern of blownfuses 96 corresponds exactly to the pattern of address bits, the senselines all block current and the voltage across the bank remains high.Otherwise, at least one sense line conducts and the voltage falls. Ahigh voltage thus indicates that the programmed address has beendetected and the redundant row or column 91 is addressed in theauxiliary array 94. A low voltage indicates that a different address hasbeen applied and a corresponding memory element in the memory array 93is addressed.

[0036]FIG. 7 is a simplified block diagram of a computer 100 using anintegrated circuit such as the memory device 90 of FIG. 6. The computer100 includes a central processing unit 103 coupled via a bus 104 to amemory and memory manager 106, function circuitry 108, user inputinterface 101 and a display 102. The central processing unit 103 carriesout instructions obtained from the memory via the memory manager 106 inresponse to input from the user input interface 101 and displays resultson the display 102. The central processing unit 103 also stores resultsin the memory via the memory manager 106.

[0037] The memory of the memory and memory manager 106 is an examplewhere embodiments of the instant invention such as the memory device 90of FIG. 6 are useful. While the present invention is particularly usefulin large memory arrays (i.e., RAM memories, particularly those having 16megabytes or more of memory) for use in personal computers andworkstations, examples of other systems where such computers 100including a memory according to embodiments of the present inventionfind application include camcorders, televisions, automobile electronicsystems, microwave ovens and other home and industrial appliances.

[0038] Although the present invention has been described with referenceto several embodiments, the invention is not limited to theseembodiments. Rather, the invention is limited only by the appendedclaims, which include within their scope all equivalent devices ormethods which operate according to the principles of the invention asdescribed. Exhibit A.-page 23 Appl. No. Atty Dkt # Applicants FiledTitle Polishing of Semiconductor Wafers 09/316,076 660073.722C1 RonnieM. Harrison May 20, 99 Synchronous Clock Generator Including aDelay-Locked Loop Signal Loss Detector 09/316,744 660073.726C1 BrentKeeth May 21, 99 Adjustable Output Driver Circuit 09/316,998660073.664D1 Roger Lee, Dennis May 24, 99 Fuse, Memory IncorporatingSame Keller, and Ralph and Method Kauffman 09/317,007 660073.654D2Charles Ingalls May 24, 99 Method and Apparatus for Strobing AntifuseCircuits in a Memory Device 09/317,059 660073.584C1 Troy Manning May 24,99 Method and Apparatus for Generating an Internal Clock Signal that isSynchronized to an External Clock Signal. 09/317,368 660073.654D1Charles Ingalls May 24, 99 Method and Apparatus for Strobing AntifuseCircuits in a Memory Device 09/318,293 660073.723C1 May 25, 99Synchronous Clock Generator Including a False Lock Detector 09/318,557660073.548D2 Donald M. Morgan May 26, 99 Programmable Voltage Dividerand Method for Testing the Impedance of a Programmable Element09/318,571 660073.548D1 Donald M. Morgan May 26, 99 Programmable VoltageDivider and Method for Testing the Impedance of a Programmable Element09/320,244 660073.548D4 Donald M. Morgan May 26, 99 Programmable VoltageDivider and Method for Testing the Impedance of a Programmable Element09/320,253 660073.548D3 Donald M. Morgan May 26, 99 Programmable VoltageDivider and Method for Testing the Impedance of a Programmable Element09/321,266 660073.775 Jim Nuxoll May 27, 99 Adjustable Coarse AlignmentTooling Julian Aberasturi for Packaged Semiconductor Devices 09/321,295660073.512C1 Jeff Wright, Hua May 27, 99 High-Speed Test System for aZheng. and Paul Memory Device Fuller 09/327,692 660073.771 Tongbi JiangJun 08, 99 Thermally Conductive Adhesive Tape He Xiping forSemiconductor Devices and Method for Using the Same 09/328,034660073.494C2 Gurtej Sandhu Jun 08, 99 Method and Apparatus for Detectingthe Endpoint in Chemical-Mechanical Polishing of Semiconductor Wafers09/328,042 660073.768 Paul D. Shirley Jun 08, 99 Resist Uniformity byControlling the Wafer Temperature with Backside Air 09/328,884660073.727C1 Brent Keeth Jun 09, 99 Adjustable Output Driver Circuit09/332,597 660073.729D1 Brent Keeth Jun 14, 99 Latching Wordline Driverfor Multi- Bank Memory 09/333,814 660073.616D1 Steven F. Schicht and Jun15, 99 Method and Apparatus for Anticipatory Jeffrey P. Wright Selectionof External or Internal Addresses in a Synchronous Memory Device09/333,818 660073.524C2 Hua Zheng and Jeff Jun 15, 99 Circuit and Methodfor Providing a Wright Substantially Constant Time Delay Over a Range ofSupply Voltages 09/336,391 660073.642C1 Thomas W. Voshell Jun 18, 99Method and Apparatus for Coupling Data From a Memory Device Using ASingle Ended Read Data Path 09/338,030 660073.578C1 Thad Brunelli Jun22, 99 Method and Apparatus for Controlling a Temperature of a PolishingPad Used in Planarizing Substrates 09/338,257 660073.648D1 Wally FisterJun 22, 99 Method and Apparatus for Generating Memory Addresses forTesting Memory Devices

What is claimed is:
 1. A method of fabricating a fuse, the methodcomprising: forming a fuse comprising a conductive material on asubstrate; forming a series of dielectric layers overlying the substrateand the fuse; forming an opening extending through the series ofdielectric layers, the opening exposing a portion of the fuse; andforming a dielectric layer on the fuse through the opening.
 2. Themethod of claim 1 wherein the step of forming a dielectric layer on thefuse includes forming a dielectric layer having a thickness of between2,000 and 3,000 angstroms on the fuse.
 3. The method of claim 2 whereinthe step of forming the dielectric layer on the fuse comprises formingthe dielectric layer on the fuse and sidewalls of the opening.
 4. Themethod of claim 1 wherein the step of forming a fuse includes forming afuse comprising tungsten silicide.
 5. The method of claim 1 wherein thestep of forming an opening includes etching the series of dielectriclayers in an anisotropic etch for a time longer than is required inorder to etch completely through the composite thickness of the seriesof dielectric layers.
 6. The method of claim 1 wherein the step offorming a series of dielectric layers includes forming a series of oxidelayers.
 7. The method of claim 1 wherein the step of forming a series ofdielectric layers includes forming a series of silicon dioxide layers.8. The method of claim 1 wherein the step of forming a fuse includes:forming a layer of polysilicon on an oxide layer disposed on thesubstrate; and forming a layer of tungsten silicide on the layer ofpolysilicon.
 9. The method of claim 1 wherein the step of forming a fuseincludes: forming a layer of polysilicon having a thickness of a 1,000angstroms on a field oxide layer disposed on the substrate; and forminga layer of tungsten silicide having a thickness of 1,200 angstroms onthe layer of polysilicon.
 10. The method of claim 1 wherein the step offorming a dielectric layer on the fuse includes forming a dielectriclayer comprising silicon dioxide on the fuse.
 11. The method of claim 1wherein the step of forming a series of dielectric layers includes:forming a first dielectric layer on the fuse; forming a seconddielectric layer on the first dielectric layer; forming a thirddielectric layer on the second dielectric layer; and forming a fourthdielectric layer on the third dielectric layer, wherein the series ofdielectric layers provide greater than four microns of compositethickness.
 12. The method of claim 11 wherein the step of forming adielectric layer on the fuse includes forming a dielectric layer havinga thickness of between 2,000 and 3,000 angstroms on the series ofdielectric layers and the fuse.
 13. The method of claim 11 wherein thestep of forming a dielectric layer on the fuse includes forming adielectric layer comprising silicon dioxide on the series of dielectriclayers and the fuse.
 14. The method of claim 11 wherein the step offorming a series of dielectric layers further includes: forming a fifthdielectric layer on the fourth dielectric layer; forming a sixthdielectric layer on the fifth dielectric layer; and forming apassivation layer on the sixth dielectric layer, wherein the series ofdielectric layers provide greater than seven microns of compositethickness.
 15. The method of claim 14 wherein the step of forming adielectric layer on the fuse includes forming a dielectric layercomprising silicon dioxide having a thickness of between 2,000 and 3,000angstroms on the passivation layer and the fuse.
 16. The method of claim1 wherein the step of forming a series of dielectric layers includes:forming a first dielectric layer comprising borophosphosilicate glasshaving a thickness in excess of one micron on the fuse; forming a seconddielectric layer comprising silicon dioxide having thickness of a micronon the first dielectric layer; forming a third dielectric layercomprising silicon dioxide having a thickness of a micron on the seconddielectric layer; and forming a fourth dielectric layer comprisingsilicon dioxide having a thickness of a micron on the third dielectriclayer.
 17. The method of claim 16 wherein the step of forming adielectric layer on the fuse includes forming a dielectric layercomprising silicon dioxide having a thickness of between 2,000 and 3,000angstroms on the series of dielectric layers and the fuse.
 18. Themethod of claim 16 wherein the step of forming a series of dielectriclayers further includes steps of: forming a fifth dielectric layercomprising silicon dioxide having a thickness of a micron on the fourthdielectric layer; forming a sixth dielectric layer comprising silicondioxide having a thickness of a micron on the fifth dielectric layer;and forming a passivation layer comprising silicon nitride on the sixthdielectric layer.
 19. The method of claim 18 wherein the step of forminga dielectric layer on the fuse includes forming a dielectric layercomprising silicon dioxide having a thickness of between 2,000 and 3,000angstroms on the passivation layer and the fuse.
 20. An apparatuscomprising: a substrate; a fuse comprising conductive material supportedby the substrate; a series of dielectric layers overlying the substrateand the fuse; an opening formed above the fuse and extending through theseries of dielectric layers at least to the fuse; and a dielectric layerformed on the fuse, the dielectric layer being fabricated separatelyfrom the fabrication of the series of dielectric layers.
 21. Theapparatus of claim 20, further comprising a dynamic random access memorycircuit formed on the substrate.
 22. The apparatus of claim 20, furthercomprising a dynamic random access memory circuit including at least 16megabytes of memory formed on the substrate.
 23. The apparatus of claim20 wherein the fuse comprises polysilicon.
 24. The apparatus of claim 20wherein the fuse comprises: a layer of polysilicon having a thickness ofa 1,000 angstroms disposed on an oxide formed on the substrate; and alayer of tungsten silicide having a thickness of 1,200 angstroms formedon the layer of polysilicon.
 25. The apparatus of claim 20 wherein theseries of dielectric layers comprises: a first dielectric layer formedon the fuse and the substrate; a second dielectric layer formed on thefirst dielectric layer; a third dielectric layer formed on the seconddielectric layer; and a fourth dielectric layer formed on the thirddielectric layer, wherein the series of dielectric layers providegreater than four microns of composite thickness.
 26. The apparatus ofclaim 25 wherein the dielectric layer formed on the fuse has a thicknessof between 2,000 and 3,000 angstroms.
 27. The apparatus of claim 25wherein the dielectric layer formed on the fuse comprises a layer ofsilicon dioxide.
 28. The apparatus of claim 20 wherein the series ofdielectric layers comprises: a first dielectric layer formed on the fuseand the substrate; a second dielectric layer formed on the firstdielectric layer; a third dielectric layer formed on the seconddielectric layer; a fourth dielectric layer formed on the thirddielectric layer; a fifth dielectric layer formed on the fourthdielectric layer; a sixth dielectric layer formed on the fifthdielectric layer; and a passivation layer formed on the sixth dielectriclayer, wherein the series of dielectric layers provide greater thanseven microns of composite thickness.
 29. The apparatus of claim 28wherein the dielectric layer formed on the fuse has a thickness ofbetween 2,000 and 3,000 angstroms.
 30. The apparatus of claim 29 whereinthe dielectric layer formed on the fuse comprises a material chosen froma group consisting of silicon dioxide and silicon nitride.
 31. Theapparatus of claim 20 wherein the series of dielectric layers comprise aseries of dielectric layers providing greater than four microns ofcomposite thickness.
 32. The apparatus of claim 31 wherein thedielectric layer formed on the fuse has a thickness of less than 3,500angstroms.
 33. The apparatus of claim 20 wherein the substrate comprisesa silicon substrate.
 34. A random access memory comprising: a substrate;random access memory circuitry formed on the substrate; a series offuses comprising conductive material supported by the substrate; aseries of dielectric layers formed on the substrate and the series offuses; an opening formed above at least one of the series of fuses andextending through the series of dielectric layers at least to the seriesof fuses; and a dielectric layer formed on the series of fuses, thedielectric layer being fabricated separately from the series ofdielectric layers.
 35. The random access memory of claim 34 wherein theseries of fuses permit redundant memory array elements to replacedefective memory array elements in the random access memory array. 36.The random access memory of claim 34 wherein each of the series of fusescomprise a layer of polysilicon formed on the substrate.
 37. The randomaccess memory of claim 36 wherein each of the series of fuses furthercomprise a layer of tungsten silicide formed on the layer ofpolysilicon, the layer of polysilicon and the layer of tungsten silicidecomprising a total thickness of between 1,800 and 2,600 angstroms. 38.The random access memory of claim 34 wherein: the series of dielectriclayers comprises a series of silicon dioxide layers having greater thanfour microns of composite thickness; and the dielectric layer formed onthe series of fuses has a thickness of between 2,000 and 3,000 angstromsand comprises a material chosen from a group consisting of silicondioxide and silicon nitride.
 39. A computer including: a centralprocessing unit coupled to a bus; an input/output interface coupled tothe bus; a read-only memory coupled to the central processing unit; anda random access memory coupled to the central processing unit, whereinthe random access memory comprises: a substrate; a random access memoryarray formed on the substrate; a series of fuses comprising conductivematerial supported by the substrate; a series of dielectric layersformed on the series of fuses and the substrate; a series of openingseach formed above at least one of the series of fuses and extendingthrough the series of dielectric layers to the series of fuses; and adielectric layer formed on the series of fuses, the dielectric layerbeing formed separately from the series of dielectric layers.
 40. Thecomputer of claim 39 wherein the series of fuses each comprise: a layerof polysilicon formed on the substrate; and a layer of tungsten silicideformed on the layer of polysilicon, the layer of polysilicon and thelayer of tungsten silicide comprising a total thickness of between 1,800and 2,600 angstroms.
 41. The computer of claim 39 wherein: the series ofdielectric layers comprises a series of silicon dioxide layers havinggreater than four microns of composite thickness; and the dielectriclayer formed on the series of fuses has a thickness of between 2,000 and3,000 angstroms and comprises a material chosen from a group consistingof silicon dioxide and silicon nitride.
 42. The computer of claim 39wherein the series of fuses permit redundant memory array elements toreplace defective memory array elements in the random access memoryarray.